The invention relates to a modified sign-magnitude DAC, and particularly to an improvement for sharing bit current determining resistors for each bit of the modified sign-magnitude DAC between internal first and second DAC sections thereof, and to a technique for balancing gains of the internal first and second DAC sections for each bit.
In a sign-magnitude DAC (digital-to-analog converter), the most significant bit of the digital input word is a "sign bit" which indicates that the remaining bits of the digital word represent a positive number if the sign bit is a "1" and a negative number if the sign bit is a "0'8. A conventional sign-magnitude DAC includes two separate internal DAC sections, one for converting positive input numbers to an analog output current voltage, the other for converting negative input numbers to a corresponding output current. The bit switches of both the two internal DAC sections are summed in the same current summing conductor. The sign bit of the digital input word is used to switch between the "positive" internal DAC section and the "negative" internal DAC section.
FIG. 4 shows an internal structure for the same bit of both the internal DAC sections for a conventional sign-magnitude DAC. Dotted line 110 encloses a typical bit circuit for one of the internal DAC sections referred to as "DACA". The DACA bit circuit includes bit switch 15,16 and a laser-trimmable bit current-determining resistor 270 and NPN transistor 17. Dotted line 120 encloses the corresponding bit circuit, of the other internal DAC section (referred to as "DACB") for the same bit. More specifically, bit 120 includes bit switch 19,20, NPN transistor or 18, and trimmable bit current determining resistor 280.
A precise bias voltage V.sub.BIAS is applied to the base electrodes of NPN transistors 17 and 18, the emitters of which apply a precise voltage across the current-determining resistors 270 and 280. Control circuitry (not shown) responsive to the digital input word applies appropriate bit switch selection signals to bit switch MOSFET gate electrodes 24 and 25, of bit switch 15,25, depending on whether the corresponding bit of the present digital input word is a "1" or a "0", if the present digital input word is a positive number. If the present digital input word is a negative number, appropriate bit selection signals are applied by the control circuitry to MOSFET gate electrodes 26 and 29 of bit switch 19,20, depending on whether the corresponding bit of the digital input word is "1" or a "0".
In conventional sign-magnitude DACs, the internal DACA and DACB sections are located in substantially separated areas of an integrated circuit chip. Bit-current determining resistors 270 and 280 therefore also are located in substantially separated chip areas. Current source transistors 17 and 18 also are located in substantially separated areas of the chip. At the present state of the art, the base-to-emitter voltages of transistors 17 and 18 may be different, often by as much as one to five millivolts, depending on the manufacturing process and transistor geometrics. Since it is essential that the "gains" of the DACA and DACB sections be identical to avoid harmonic distortion of output signals produced in response to input signals such as digital audio input signals, bit current determining resistors 270 and 280 must be trimmed or adjusted during manufacture to compensate for the above differences in the base-to-emitter voltages of transistors 17 and 18, and also to compensate for process-dependent differences in the values of resistors 270 and 280. The more adjustability or "trimmability" that is needed for bit-current-determining resistors, the larger is the amount of chip area that they must occupy. Furthermore, the more transistors there are in an integrated circuit, and the greater the spacing between transistors thereon which need to be precisely matched, the more susceptible the integrated circuit is to parameter shifts induced by the integrated circuit packaging process being used.
There is a presently unmet need for a DAC capable of converting positive and negative input digital numbers to a corresponding AC analog output signal in as little chip area as possible, with balanced gain of the internal "DACA" and "DACB" sections to reduce harmonic distortion of the digital input word as much as possible.